RISC-V: ARM’s competing architecture passes the 5nm engraving course

In a world dominated by ARM, the rising RISC-V architecture begins to take serious shape with the announcement by SiFive and TSMC of the first design validation (tape out) engraved in 5 nm. While the chip is yet to be manufactured, this milestone in production shows that RISC-V processors are ready to roll off lines using cutting-edge etching methods.

While SiFive develops the plans for cores, CPUs and other SoC plans based on RISC-V, its subsidiary OpenFive is in charge of the integration and manufacturing part with partners such as TSMC. The first “state-of-the-art” chip thus validated integrates 32-bit RISC-V cores (SiFive E76) and is not lagging behind on the technical side: 2.5D packaging, ultra-fast HBM3 memory, etc. If the chip should not be produced as it is, this 5nm “tape-out” proves that a complex, modern and ultra-fine-etched RISC-V SoC is now real.

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An announcement that echoes that of Intel last month. When announcing Intel Foundry Services, the giant clearly cited RISC-V as one of the ISAs that its new service could produce. Two announcements one month apart which put RISC-V side by side and the giants TSMC and Intel. Enough to strengthen its legitimacy in the face of an ARM whose takeover by Nvidia makes many manufacturers and governments cringe.

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While RISC-V still has a long way to go to catch up with ARM – development and production software tools, design variety and performance, etc. – each advertisement which passes places him in the most serious competitor of ARM.

Source : Tom’s Hardware US

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